Processor control system for supplying control instructions to a processor

ABSTRACT

A processor control system allows stored program code to be replaced. The original code can be stored entirely in a first memory, for example a ROM, with correction instructions stored in a second memory, for example a RAM, and the second memory is accessed only when a correction instruction exits. Received memory addresses are divided into a first plurality of most significant bits, and a second plurality of least significant bits. Only when the second plurality of least significant bits are all equal to zero, and there is a correction instruction stored in the RAM with an address which equals the most significant bits, the correction instruction is read and supplied to the processor. This, employs relatively little additional hardware, and the efficiency of the system is improved.

TECHNICAL FIELD OF THE INVENTION

This invention relates to a processor control system, and in particularto a system for supplying control instructions to a processor, allowingcorrection of those instructions when required.

BACKGROUND OF THE INVENTION

Many electronic devices include embedded processors, which operate onthe basis of program data supplied thereto. The devices thereforeinclude means for storing the program data. Typically, the means forstoring the program data is a read-only memory (ROM), as this istypically the most efficient type of storage available.

However, storing the program data entirely on ROM has the disadvantagethat the system becomes inflexible, in that it is not possible to updateor correct the stored program data.

U.S. Pat. No. 5,592,613 discloses a microprocessor with a program memoryand a program correction circuit. The program correction circuitincludes an electrically programmable nonvolatile memory for storingaddress data and correction program data. The stored address data denotethe addresses in the program memory where the stored program data is tobe replaced by the correction program data.

However, this has the disadvantage that each address supplied to thesystem must be compared with the address data stored in the nonvolatilememory, which can compromise the speed of the processor.

U.S. Pat. No. 4,751,703 discloses a method of storing the control codefor a processor, using a ROM, as well as a read/write memory (in theform of a random access memory RAM) which includes a code area and apatch area. Thus, the control code is virtually divided into a number ofblocks, with the first instruction of each block stored in the code areaof the RAM, and the subsequent instructions of each block stored in theROM. When it is determined that a block of code contains an error, thefirst instruction of that block, stored in the RAM, can be replaced by abranch instruction, which causes subsequent instructions to be read fromthe patch area of the RAM. The patch can then be stored in the RAM, withthe final instruction of the patch returning the control to the previouscontrol code.

However, this system has the disadvantage that the RAM needs to beaddressed once in each block of code, which is relatively inefficientwhen there are no corrections to implement.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a processorcontrol system in which, by employing relatively little additionalhardware, the efficiency of the system can be improved.

In particular, the original code can be stored entirely in a firstmemory, for example a ROM, with correction instructions stored in asecond memory, for example a RAM, and the second memory is accessed onlywhen a correction instruction exists. Received memory addresses aredivided into a first plurality of most significant bits, and a secondplurality of least significant bits. Only when the second plurality ofleast significant bits are all equal to zero, and there is a correctioninstruction stored in the RAM with an address which equals the mostsignificant bits, the correction instruction is read and supplied to theprocessor.

This has the advantage that the additional power consumption is low whenthere is no correction instruction stored.

This has the further advantage that the system does not require anyarbitrary address comparisons to determine the locations for whichcorrection instructions exist, and so the processor speed is notcompromised.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block schematic diagram of a system according to the presentinvention.

FIG. 2 is a block schematic diagram of a part of the system of FIG. 1.

FIG. 3 is a block schematic diagram of an alternative system accordingto the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a block schematic diagram, showing a system in accordance withan aspect of the present invention. The system receives inputs on aninput line 10, and provides output instructions to a processor (notshown) on an output line 12. The inputs take the form of N bit addressesA(N−1:0), the notation A(N−1:0) meaning that the (N−1)th bit is the mostsignificant bit of the address and the 0th bit is the least significantbit of the address.

Program code for the processor is stored in a ROM 14, which has 2^(N)locations, corresponding to the 2^(N) possible N bit addresses. When anaddress A(N−1:0) is received on the input line 10, the instructionstored at the corresponding memory location is read out, and supplied toa multiplexer 16, which usually passes the signal from the ROM 14 to theprocessor.

Thus, when there are no corrections to the original program code, it canbe read out continuously from the ROM 14. However, the system alsoincludes means for storing and reading correction instructions.Specifically, the system also includes a RAM 18, and a flag setting anddecoding circuit 20. The RAM 18 has 2^(N−M) locations, addressed by the(N−M) most significant bits of the addresses received on the input line10.

The flag setting and decoding circuit 20 also receives the N bitaddresses received-on the input line 10. As will be described in moredetail with respect to FIG. 2, a flag is set whenever a correctioninstruction is stored. The flag setting and decoding circuit 20 testswhether the M least significant bits of an input address are zero, andalso tests whether a flag has been set for the (N−M) most significantbits of that address. If so, the RAM 18 is enabled, the instructionstored in the RAM is read out, and the multiplexer 16 is controlled topass the signal from the RAM 18 onto the output line 12.

FIG. 2 shows in more detail the form of the flag setting and decodingcircuit 20. The received address A(N−1:0) is divided into its M leastsignificant bits A(M−1:0) and its N−M most significant bits A(N−1:M).The least significant bits are supplied to a block 22, where it isdetermined whether all of the bits are equal to zero. If so, a binary 1is passed to an AND gate 24. Otherwise, a binary 0 is passed to the ANDgate 24. The most significant bits are passed to a decoding block 26,which resolves the N−M bit inputs into 2^(N−M) outputs. When acorrection instruction is stored in the RAM 18 at a particular N−M bitaddress, a flag is set in a corresponding latch 28. Any flag is suppliedto a respective AND gate 30, which also receives an input from thedecoding block 26.

Thus, when the decoding block 26 determines that a specific one of theAND gates 30 has been selected by the N−M bit address, and a flag hasbeen set on the corresponding latch 28, the respective AND gate 30supplies an output to a block 32. The block 32 provides an output signalwhen it receives a signal from one of the AND gates 30, and an outputsignal from the block 32 is provided to a second input of the AND gate24.

Thus, if a flag has been set, the AND gate 24 provides an output signalwhen the M least significant bits of the address A(M−1:0) are all equalto zero, and the N−M most significant bits of the address A(N−1:M)correspond to the latch 28 on which the flag has been set.

In that case, the output signal from the AND gate 24 is supplied to theRAM 18 to enable it, and also to the multiplexer 16, so that theinstruction read from the RAM 18 is supplied to the processor.

It should be noted that the multiplexer 16 can be omitted from thesystem if the RAM and ROM both have a high output impedance when notenabled. An enabling signal for the RAM 18 would correspond to anon-enabling signal for the ROM 14, and consequently, the high outputimpedance of the ROM 14 would ensure that it is the output from the RAM18 that is supplied to the processor. Conversely, when the ROM 14 isenabled, the high output impedance of the RAM 18 ensures that the outputfrom the ROM 14 is supplied to the processor.

As mentioned above, a flag is set when a correction instruction isstored in the RAM 18. For example, the decode circuit 26 may also beused to set any flags.

As described so far, the decode circuit 26 is active at all times, butit will be apparent that an output is provided from the AND gate 24 foronly a small proportion of the time. Therefore, to save power, thedecode circuit 26 can be enabled only when the comparison circuit 22produces an output indicating that the M least significant bits of theaddress are all zero. This ensures that the decode circuit block 26 willbe active only at times when the RAM can be activated.

The instructions stored in the RAM 18 can advantageously beunconditional jump instructions, specifying a memory location at whichreplacement code can be stored. For example, the memory location can bein a separate RAM or non-volatile memory (such as a Flash memory), whichmay already be provided on the device for another purpose.

FIG. 3 shows an alternative embodiment of the invention, in whichreference numerals which are the same as reference numerals used in FIG.1 indicate similar components.

In this case, the M least significant bits (M−1:0) of the receivedaddress (N−1:0) are supplied to a comparison block 22, which provides anoutput when all of these bits are zero. The output is supplied to an ANDgate 36. In order to test whether a correction instruction has beenstored in the RAM 18, an output from the RAM 18 itself is examined.Specifically, if the correction instructions take the form ofunconditional jump instructions, as described above, then it will bepossible to rely on the fact that one specific bit of the data stored inthe RAM 18 (identified here as “B”) will take the binary value 1 if, andonly if, a correction instruction is stored at that address in the RAM18.

The bit “B” is supplied on line 38 to the second input of the AND gate36, which therefore controls the multiplexer 16 to supply the outputfrom the RAM 18 to the processor, only if the M least significant bitsof the address A(M−1:0) are all equal to zero, and the N−M mostsignificant bits of the address A(N−1:M) define an address in the RAM 18at which a correction instruction has been stored.

In a further modification of the system shown in FIG. 3, the RAM 18 mayhave a field which is one bit wider than is required to store thecorrection instructions. In that case, the extra bit can be used as thebit “B”, and used to store a flag bit, when a correction instruction isstored at that address.

There is therefore described a system which allows replacement ofprogram code, without having a large adverse effect on the performanceof the processor or the rest of the device.

1. A processor control system, for use with a processor, the controlsystem comprising: means for receiving a sequence of addresses, eachaddress comprising first and second pluralities of address bits; a firstmemory, for containing a set of instructions for the processor at memorylocations in said first memory corresponding to all of said addresses; asecond memory, suitable for containing only correction instructions forthe processor at memory locations in said second memory corresponding torespective combinations of said first plurality of address bits; meansfor determining, for each received address, when all of said secondplurality of address bits in the received address are equal to zero,and, in that event, for determining whether the second memory contains acorrection instruction at the memory location corresponding to saidfirst plurality of address bits in said received address; and means forsupplying an output instruction in response to each received address,the output instruction being a correction instruction read from thesecond memory in the event that all of said second plurality of addressbits in a received address are equal to zero and it is determined thatthe second memory contains a correction instruction at the memorylocation corresponding to said first plurality of address bits in saidreceived address, and the output instruction otherwise being read fromthe first memory.
 2. A processor control system as claimed in claim 1,further comprising: a multiplexer, connected to receive instructionsread from the first memory and the second memory, and further connectedto receive a control signal, and being adapted to output theinstructions from the either the first memory or the second memory, independence on the control signal.
 3. A processor control system asclaimed in claim 2, further comprising: means for generating a controlsignal for said multiplexer, the control signal being such that theoutput instruction is the instruction read from the second memory in theevent that all of said second plurality of address bits in a receivedaddress are equal to zero and it is determined that the second memorycontains a correction instruction at the memory location correspondingto said first plurality of address bits in said received address, andthe output instruction is otherwise the instruction read from the firstmemory.
 4. A processor control system as claimed in claim 1 furthercomprising: a third memory, for storing replacement code, wherein thesecond memory is suitable for containing correction instructions in theform of unconditional jump instructions specifying addresses in thethird memory.
 5. A processor control system as claimed in claim 1,further comprising: means for setting a flag when a correctioninstruction is stored in the second memory; and wherein the means fordetermining whether the second memory contains a correction instructionat the memory location corresponding to said first plurality of addressbits in said received address comprises means for testing whether therespective flag has been set.
 6. A processor control system as claimedin claim 5, wherein the means for testing whether the respective flaghas been set is disabled unless it is determined that all of said secondplurality of address bits in a received address are equal to zero.
 7. Aprocessor control system as claimed in claim 5, wherein the secondmemory is suitable for containing at each memory location a correctioninstruction and a flag bit, which is set only when the memory locationcontains a correction instruction, and wherein the means for testingwhether the respective flag has been set comprises means for testing thevalue of said flag bit.
 8. A processor control system as claimed inclaim 1, wherein the means for determining whether the second memorycontains a correction instruction at the memory location correspondingto said first plurality of address bits in said received addresscomprises means for testing the value of a specific bit at said memorylocation, wherein the specific bit takes a particular value in all caseswhen the second memory contains a correction instruction at said memorylocation.
 9. A processor control system, for use with a processor, thecontrol system comprising: an input line for receiving a sequence of Nbit addresses, each address comprising M least significant address bitsand N−N most significant address bits; a read only memory (ROM), forcontaining a set of instructions for the processor at memory locationsin said ROM corresponding to all of said addresses; a random accessmemory (RAM), suitable for containing only correction instructions forthe processor at memory locations in said RAM corresponding torespective combinations of said most significant address bits; a flagsetting and decoding circuit for determining, for each address receivedon the input line, when all of said least significant address bits inthe received address are equal to zero, and, in that event, fordetermining whether the RAM contains a correction instruction at thememory location corresponding to said most significant address bits insaid received address; and means for supplying an output instruction inresponse to each received address, the output instruction being acorrection instruction read from the RAM in the event that all of saidleast significant address bits in a received address are equal to zeroand it is determined that the RAM contains a correction instruction atthe memory location corresponding to said most significant address bitsin said received address, and the output instruction otherwise beingread from the ROM.
 10. A processor control system as claimed in claim 9,further comprising: a multiplexer, connected to receive instructionsread from the first memory and the second memory, and further connectedto receive a control signal, and being adapted to output theinstructions from the either the first memory or the second memory, independence on the control signal.
 11. A processor control system asclaimed in claim 10, further comprising: means for generating a controlsignal for said multiplexer, the control signal being such that theoutput instruction is the instruction read from the second memory in theevent that all of said second plurality of address bits in a receivedaddress are equal to zero and it is determined that the second memorycontains a correction instruction at the memory location correspondingto said first plurality of address bits in said received address, andthe output instruction is otherwise the instruction read from the firstmemory.
 12. A processor control system as claimed in claim 9 furthercomprising: a third memory, for storing replacement code, wherein thesecond memory is suitable for containing correction instructions in theform of unconditional jump instructions specifying addresses in thethird memory.
 13. A processor control system as claimed in claim 9,further comprising: means for setting a flag when a correctioninstruction is stored in the second memory; and wherein the means fordetermining whether the second memory contains a correction instructionat the memory location corresponding to said first plurality of addressbits in said received address comprises means for testing whether therespective flag has been set.
 14. A processor control system as claimedin claim 13, wherein the means for testing whether the respective flaghas been set is disabled unless it is determined that all of said secondplurality of address bits in a received address are equal to zero.
 15. Aprocessor control system as claimed in claim 13, wherein the secondmemory is suitable for containing at each memory location a correctioninstruction and a flag bit, which is set only when the memory locationcontains a correction instruction, and wherein the means for testingwhether the respective flag has been set comprises means for testing thevalue of said flag bit.
 16. A processor control system as claimed inclaim 9, wherein the means for determining whether the second memorycontains a correction instruction at the memory location correspondingto said first plurality of address bits in said received addresscomprises means for testing the value of a specific bit at said memorylocation, wherein the specific bit takes a particular value in all caseswhen the second memory contains a correction instruction at said memorylocation.
 17. A processor control system, for use with a processor, thecontrol system comprising: an input line for receiving a sequence of Nbit addresses, each address comprising M least significant address bitsand N−M most significant address bits; a read only memory (ROM), forcontaining a set of instructions for the processor at memory locationsin said ROM corresponding to all of said addresses; a random accessmemory (RAM), suitable for containing only correction instructions forthe processor at memory locations in said RAM corresponding torespective combinations of said most significant address bits; a flagsetting and decoding circuit for determining, for each address receivedon the input line, when all of said least significant address bits inthe received address are equal to zero and for setting a flag when acorrection instruction is stored in the RAM corresponding to said mostsignificant address bits in said received address; a multiplexer,connected to receive instructions read from the ROM and the RAM and acontrol signal, the control signal controlling output instructions ofthe multiplexer such that the output instruction may contain: theinstruction read from the RAM in the event that: a) all of said leastsignificant address bits in a received address are equal to zero; and b)the flag has been set; or otherwise the instruction read from the ROM.